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Discuss the concept of Physical Design, ASIC design flow (RTL-to-GDS) Demonstrate the core features of IC Compiler which is used during the course; Generate a GDS from an RTL design; Skills Needed: Basic knowledge of backend design flow. Hands-on experience with Linux/Unix will be required for lab exercises..

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Traditionally, CDC verification has been carried out on RTL descriptions on the basis that appropriate directives inserted in the RTL will ensure reliable data synchronizers are inserted into the netlist by synthesis. But a number of factors are coming together that demand a re-evaluation of this assumption.

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